Q:

Edge-triggered flipflops - keep CP high or low, most of the time?

I'm using 74HCT574 Octal D-type flipflops in a homebrew-cpu project. http://assets.nexperia.com/documents/data-sheet/74HC_HCT574.pdf
These flip-flops latch their input on a +ve edge on CP.
I could either:

keep CP high, then pull it down for the clock cycle before I want it to latch.
keep CP low, then pull it up for the clock cycle after I want it to latch.

Option 1 looks easier to write microcode for, as CP is pulled down in the same cycle as the input is set-up for the flip-flop.
Are there issues with using option 1?
How do professionals use the CP input on flipflops?  (If any still do, since we have $2 CPLDs and MCUs.)

A:

If you have a pull-up or -down resistor on the CP signal, you could save some power by making the idle state the state where no current flows.
If there is noise in your environment, and you can predict its effect (this is unlikely to be the case), then you could reduce the risk of disturbances by making the idle state the state that is less affected by the noise.
But otherwise, it does not matter at all.
For normal CMOS inputs and outputs, low and high signals behave pretty much symmetrically. For TTL, the levels are not symmetrical, but that does not matter if you interface only with other (TTL-compatible) CMOS devices.
Use whatever makes the rest of your circuit or your software simpler.

