Q:

systemverilog assertion - how to ignore first event after reset

I have written following assertion:
    assert property(@(posedge ClkRs_ix.clk) 
        disable iff (ClkRs_ix.reset) $stable(Signal_ia)[*20] |-> 
        (Signal_oq==Signal_ia));

I wanted to express that 20 clock cycles for which the input signal is stable, at the 21st cycle the output has to have the same value as input.
This one works, but only if I assure no changes in the state of Signal_ia during the reset. If I assert reset, change the state of Signal_ia, then release the reset, this condition always fails. This usually happens when I start the simulation with Signal_ia = 'X' and during reset it becomes '0'.
Is there any way how to write this better? Resp. is there a way how to ignore first event after reset, as it might be tripping due to conditions happening at reset? If I understood well, iff assures, that this assertion is ignored during reset. Effects I'm trying to describe have some latency, ideally I would need to ignore this condition not only in reset, but as well 20 cycles following the deassertion of the reset state.
thanks
.d.

A:

One way is to use a cascaded implication operator:
assert property(@(posedge ClkRs_ix.clk) 
    disable iff (ClkRs_ix.reset) $stable(Signal_ia)[*20] |-> 
    $stable(Signal_ia)[*20] |-> (Signal_oq==Signal_ia));

Implication operators are right-associative so 
A |-> B |-> C

is equivalent to
A |-> (B |-> C)

In other words, don't check B |-> C until A has occurred.
Another way to achieve this would be to use satellite code. Satellite code is code written in the host language, which aids the assertion. So, you could write an FSM that detects the first occurrence of the the first 'event' then enabling the assertion. If you want to be able to check the assertion in a formal tool, make sure you make the satellite code synthesisable.

