Q:

Can you make an asynchronous counter count in Gray Code?

I will firstly explain my situation and then ask a few question in the clearest way possible. I am a total beginner and thanks for coping with me. 
The Task:
I was given the task of designing a decade counter using J-K Flip-Flops. What I immediately thought of was whether I should make it Synchronous or Asynchronous. And here is where I started getting confused. 
What I know:
Now, the main advantage (that I am aware of) of synchronous over asynchronous counters is that they are more reliable, as in they do not have propagation delays, which can make an output go from 
  0111 (7) --> 1111 (15) --> 1011 (11) --> 1001 (9) --> 1000 (8)    (transiently) otherwise, they are more complex to design and generally require more circuitry. 
My Questions:
So, can an asynchronous counter count in Gray Code? And would it solve this propagation delay problem? I thought this would make any propagation delay irrelevant, because, for example, a number would change from 0100 (7) to 1100 (8) without going through transient states no matter what delays are present in the circuit. This would, in turn, make the asynchronous counter the better choice.
Also, what are the advantages of using T-type FF over D-type FF? (both being  realised in JK FF)

I must also say that the clock's frequency is really low (1Hz), Will any of this matter in this case?
THANKS SO MUCH FOR HELPING

A:

It's possible, and not overly difficult, to design an asynchronous counter which takes a two-bit gray code input and produces a three-bit graycode as output.  Such stages may be cascaded to arbitrary depth to yield an arbitrary-length gray code counter.  An interesting feature of such a counter is that unlike normal binary ripple counters, it can count in both directions equally well, and will tolerate momentary instability or metastability on either input, provided that no input changes unless the other input is stable.

simulate this circuit – Schematic created using CircuitLab
When In0 is 0, output 2 will switch if needed to make (In1 xor Out1 xor Out2) be 0.  When In0 is 1, output 1 will switch if needed to make (In1 xor Out1 xor Out2) be zero.  If In0 is stable, junk on In1 will cause junk to appear on either Out1 or Out2, but the other output will remain stable.  Once In1 stabilizes, its corresponding output will stabilize as well.  If In1 is stable, nothing besides Out0 will switch in response to In0, so noise on In0 will have no effect provided that it stabilizes before In1 changes.
Note that the design shown may have some practical considerations such as logic hazards with muxes or the lack of a reset signal; those are addressed as exercises for the reader.

