Q:

explicity chain dependency in Makefile

What's the pattern to follow when specialized Makefiles in a directory depends on the main one in a parent dir?
i have:
/
/Makefile
/src
/src/Makefile
/tests
/tests/Makefile

in /Makefile i have:
TESTING_COMMAND=something
dotest1:
    make -C tests/ $@

in /tests/makefile i have
dotest1:
    $(TESTING_COMMAND) $?

if i run:
me@host:/ $ Make dotest1

it works. but if i execute from the tests dir:
me@host:/tests/ $ Make dotest1

it will try to execute the test file in the shell, because $(TESTING_COMMAND) is empty, so it's first argument became the command passed to the shell.
I don't necessarily need that to work if executed in the /tests/ or /src/ dir, but need a way to gracefully fail.

A:

Your design scares me, but this will do the trick in the main Makefile:
TESTING_COMMAND=something
dotest1:
    make -C tests/ $@ TESTING_COMMAND=$(TESTING_COMMAND)

If you want tests/Makefile to fail well, you have a couple of options. If only that one target depends on TESTING_COMMAND, you can have it print a warning and do nothing:
ifdef TESTING_COMMAND
dotest1:
    $(TESTING_COMMAND) $?
else
dotest1:
    @echo warning: TESTING_COMMAND not defined
endif

Or if the whole Makefile depends on it, you can have Make print a warning or abort:
ifndef TESTING_COMMAND
$(warning TESTING_COMMAND is undefined, but Make will try to us it anyway)
$(error TESTING_COMMAND is undefined, Make will now abort)
endif

You can also have it abort the sub-make (the one that runs tests/Makefile) but still continue running the Make process that invoked it, but that's kind of a pain.

