Q:

Concatenation in Verilog seemingly not using full width

Source code:
module main();
wire [31:0] a = 32'b0;
wire [25:0] a_man = {1'b1, a[24:0]};
initial begin
$display("%b\n%b\n%b", {1'b1,a[24:0]}, a_man[25:0], a_man);
end
endmodule

Actual output:
% iverilog dings.v && vvp a.out
10000000000000000000000000
1xxxxxxxxxxxxxxxxxxxxxxxxx
1xxxxxxxxxxxxxxxxxxxxxxxxx

I do not understand how come all bits of a_man are not assigned. I do not understand what the difference is, between doing the concatenation inline and doing it in the wire declaration.

A:

With experience you will learn not to trust any Verilog simulator at time 0. Always allow a minimum timestep for the simulator to assign your initial value.
module test;
wire [7:0] a     = 7'b0;
wire [7:0] a_man = {1'b1, a[6:0]};

initial begin
  $display("%b %b %b", {1'b1,a[6:0]}, a_man[7:0], a_man);
  #1fs;
  $display("%b %b %b", {1'b1,a[6:0]}, a_man[7:0], a_man);
  #1ns;
  $display("%b %b %b", {1'b1,a[6:0]}, a_man[7:0], a_man);
end
endmodule

Gives (ncsim):
1xxxxxxx xxxxxxxx xxxxxxxx
10000000 1xxxxxxx 1xxxxxxx
10000000 10000000 10000000

A:

At modelsim SE-64 10.1d I have:
ModelSim> vsim work.main
# vsim work.main 
# ** Note: (vsim-3812) Design is being optimized...
# Loading work.main(fast)
run
# 10000000000000000000000000
# 10000000000000000000000000
# 10000000000000000000000000

As expected...
So: it's a tool issue, not a language one.

