An exploratory Process Variation Net Scanning (PVNS) approach to estimate interconnect delay variations is presented.
It is shown that the geometrical response of lithographic nonidealities can be quickly predicted to first order with Pattern
Matching. This concept can be extended to other process nonidealities by developing Maximum Lateral Impact
Functions to capture the effects of variations in conductor sidewall angle and thickness from etch and CMP processes.
The geometrical response for each variation can then be used to model the effective change in resistance and capacitance
and perturb the corresponding values in the extracted netlist. The impact of PVNS is demonstrated using a 90nm digital
design, and the runtime analysis indicates that this approach may potentially be twice as fast as traditional extraction.
This allows for fast electrical analysis of independent process variations on different interconnect layers instead of
traditional best and worst case corner analyses.