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[[ext:zicntr]]
=== ext:zicntr[] Extension for Base Counters and Timers
[#norm:Zihpm_op_sz_mode_acc_count]#RISC-V ISAs provide a set of up to thirty-two 64-bit performance
counters and timers# that are [#norm:Zihpm_op_sz_mode_acc_priv]#accessible via unprivileged XLEN-bit
read-only CSR registers `0xC00`–`0xC1F`# ([#nor... | riscv-isa-manual/src/unpriv/zicntr.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 9,845 |
[[ext:zve32f]]
=== ext:zve32f[] Vector Extension for Single-Precision Floating-Point
This section describes ext:zve32f[], the vector extension for
single-precision floating-point.
It is compatible with all currently defined base ISAs.
[#norm:Zve32f_Zve64f_dependent_F]#The ext:zve32f[] extension depends on the ext:zve... | riscv-isa-manual/src/unpriv/zve32f.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 758 |
[[ext:zalrsc]]
=== ext:zalrsc[] Extension for Load-Reserved/Store-Conditional Instructions
include::images/wavedrom/load-reserve-st-conditional.edn[]
Complex atomic memory operations on a single memory word or doubleword
are performed with the load-reserved (insn:lr[]) and store-conditional (insn:sc[])
instructions. ... | riscv-isa-manual/src/unpriv/zalrsc.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 16,279 |
[[zc]]
== Compressed Instructions
This chapter describes the RISC-V compressed instruction-set
extensions, which reduce static and dynamic code size by
adding short 16-bit instruction encodings for common operations.
Typically, 50%-60% of the RISC-V instructions in a program can be replaced
with compressed instruction... | riscv-isa-manual/src/unpriv/zc.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 1,164 |
[[cmo]]
=== Cache Management Operations (CMOs)
[#intro-cmo,reftext="Introduction"]
==== Introduction
_Cache management operation_ (CMO) instructions perform operations on
copies of data in the memory hierarchy. In general, CMO instructions operate on
cached copies of data, but in some cases, a CMO instruction may ope... | riscv-isa-manual/src/unpriv/cmo.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 41,499 |
[[app:mm-explanatory]]
=== RVWMO Explanatory Material
This section provides more explanation for RVWMO
<<memorymodel>>, using more informal
language and concrete examples. These are intended to clarify the
meaning and intent of the axioms and preserved program order rules. This
appendix should be treated as commentary... | riscv-isa-manual/src/unpriv/mm-explanatory.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 78,297 |
[appendix]
[[app:naming]]
== ISA Extension Naming Conventions
This chapter describes the RISC-V ISA extension naming scheme that is
used to concisely describe the set of instructions present in a hardware
implementation, or the set of instructions used by an application binary
interface (ABI).
[NOTE]
====
The RISC-V I... | riscv-isa-manual/src/unpriv/naming.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 10,260 |
[[ext:zbkb]]
=== ext:zbkb[] Extension for Bit Manipulation for Cryptography
This extension contains instructions essential for implementing
common operations in cryptographic workloads.
[[norm:Zbkb_insns_tbl]]
[%header,cols="^1,^1,4,8"]
|===
|RV32
|RV64
|Mnemonic
|Instruction
| {check}
| {check}
| insn:rol[]
| <<in... | riscv-isa-manual/src/unpriv/zbkb.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 1,076 |
[[ext:zmmul]]
=== ext:zmmul[] Extension for Integer Multiplication
(((MUL, Zmmul)))
[[norm:Zmmul_insns]]
The ext:zmmul[] extension implements the multiplication subset of the ext:m[]
extension. It adds the following instructions defined in extlink:m[]:
insn:mul[], insn:mulh[], insn:mulhu[], insn:mulhsu[], and (for RV6... | riscv-isa-manual/src/unpriv/zmmul.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 1,081 |
[[ext:zihpm]]
=== ext:zihpm[] Extension for Hardware Performance Counters
[#norm:hpmcounter_op_sz_mode]#The ext:zihpm[] extension comprises up to 29 additional unprivileged 64-bit
hardware performance counters, csr:hpmcounter3[]-csr:hpmcounter31[].# [#norm:hpm_counter_op_sz_mode_xlen32]#When
XLEN=32, the upper 32 bits... | riscv-isa-manual/src/unpriv/zihpm.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 2,573 |
[[ext:zve64x]]
=== ext:zve64x[] Vector Extension for 64-bit Integer
This section describes ext:zve64x[], the vector extension for 8-, 16-,
32-, and 64-bit integer and fixed-point types.
It is compatible with all currently defined base ISAs.
[#norm:Zve32f_Zve64x_dependent_Zve32x]#ext:zve64x[] depends upon the ext:zve3... | riscv-isa-manual/src/unpriv/zve64x.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 1,810 |
[[rv32e]]
=== RV32E and RV64E Base Integer Instruction Sets
This section describes the RV32E and RV64E base integer
instruction sets, designed for microcontrollers in embedded systems.
RV32E and RV64E are reduced versions of RV32I and RV64I, respectively:
the only change is to reduce the number of integer registers to... | riscv-isa-manual/src/unpriv/rv32e.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 1,963 |
[[ext:zfh]]
=== ext:zfh[] Extension for Half-Precision Floating-Point
This chapter describes the ext:zfh[] standard extension for _half-precision_
floating-point, which adds computational instructions compliant with the IEEE
754-2008 arithmetic standard's binary16 format and operations. The ext:zfh[] extension
depends... | riscv-isa-manual/src/unpriv/zfh.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 6,275 |
[[memorymodel]]
=== RVWMO Memory Consistency Model
(((design, high performance))) (((design, scalable)))
This section defines the base RISC-V memory consistency model. A memory
consistency model is a set of rules specifying the values that can be
returned by loads of memory. RISC-V uses a memory model called RISC-V
We... | riscv-isa-manual/src/unpriv/rvwmo.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 29,620 |
[[ext:zabha]]
=== ext:zabha[] Extension for Byte and Halfword Atomic Memory Operations
The ext:zaamo[] and ext:zacas[] extensions offer atomic memory operation (AMO) instructions for _words_,
_doublewords_, and _quadwords_ (only for insn:amocas[]). The absence of atomic
operations for subword data types necessitates e... | riscv-isa-manual/src/unpriv/zabha.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 3,957 |
[[app:atomics-examples]]
=== Atomics Assembly Code Examples
The following examples are provided as non-normative text to help explain the
RISC-V atomics ISA.
==== Compare-and-Swap Using LR/SC
insn:lr[]/insn:sc[] can be used to construct lock-free data structures. An
example using insn:lr[]/insn:sc[] to implement a c... | riscv-isa-manual/src/unpriv/atomics-examples.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 4,854 |
[[ext:zclsd]]
=== ext:zclsd[] Extension for Compressed Load/Store Pair Instructions
The ext:zclsd[] extension provides compressed load/store pair instructions for
RV32, reusing the existing RV64 doubleword load/store instruction encodings.
ext:zclsd[] depends on ext:zilsd[] and ext:zca[]. It has overlapping encodings... | riscv-isa-manual/src/unpriv/zclsd.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 5,109 |
[[za]]
== Atomic Instructions
NOTE: This chapter is currently being restructured.
Its contents are normative, but the presentation might appear disjoint.
RISC-V provides several extensions that atomically read-modify-write memory to
support synchronization between multiple RISC-V harts running in the same
memory spac... | riscv-isa-manual/src/unpriv/za.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 3,130 |
[[ext:zbb]]
=== ext:zbb[] Extension for Basic Bit Manipulation
==== Logical with negate
[%header,cols="^1,^1,4,8"]
|===
|RV32
|RV64
|Mnemonic
|Instruction
|{check}
|{check}
|insn:andn[rd,rs1,rs2]
|<<#insns-andn>>
|{check}
|{check}
|insn:orn[rd,rs1,rs2]
|<<#insns-orn>>
|{check}
|{check}
|insn:xnor[rd,rs1,rs2]
|<<#i... | riscv-isa-manual/src/unpriv/zbb.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 4,443 |
[[ext:zilsd]]
=== ext:zilsd[] Extension for Load/Store Pair Instructions
The ext:zilsd[] extension provides load/store pair instructions for RV32, reusing the existing RV64 doubleword load/store instruction encodings.
[#norm:Zilsd_reg_pairs]#Operands containing `src` for store instructions and `dest` for load instruc... | riscv-isa-manual/src/unpriv/zilsd.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 5,539 |
[[app:bitmanip-examples]]
=== Bit Manipulation Assembly Code Examples
The following examples provide software optimization guidance.
==== `strlen`
The insn:orc.b[] instruction allows for the efficient detection of `NUL` bytes in an XLEN-sized chunk of data:
* the result of insn:orc.b[] on a chunk that does not con... | riscv-isa-manual/src/unpriv/bitmanip-examples.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 3,492 |
[[ext:zce]]
=== ext:zce[] Extension for Enhanced Instruction Compression
This section describes the ext:zce[] extension, which incorporates the
compressed instruction-set extensions designed for microcontrollers.
Unlike the ext:c[] extension, the ext:zce[] extension includes extensions
that trade performance for code ... | riscv-isa-manual/src/unpriv/zce.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 609 |
[[ext:m]]
=== ext:m[] Extension for Integer Multiplication and Division
This chapter describes the standard integer multiplication and division
instruction extension, which is named ext:m[] and contains instructions
that multiply or divide values held in two integer registers.
[NOTE]
====
We separate integer multiply... | riscv-isa-manual/src/unpriv/m-st-ext.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 6,348 |
[[ext:za128rs]]
=== ext:za128rs[] Extension for Reservation-Set Size
[[norm:Za128rs_res_set_req]]
The ext:za128rs[] extension requires that the reservation sets used by the
instructions in the ext:zalrsc[] extension be contiguous, naturally aligned, and at
most 128 bytes in size.
[[ext:za64rs]]
=== ext:za64rs[] Exten... | riscv-isa-manual/src/unpriv/zars.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 661 |
[[ext:zcmt]]
=== ext:zcmt[] Extension for Compressed Table Jumps
The ext:zcmt[] extension adds table-jump instructions, which improve code density
when procedures have many call sites.
It also adds the csr:jvt[] CSR.
The csr:jvt[] CSR requires a state enable if ext:smstateen[] is implemented. See
<<csrs-jvt>> for deta... | riscv-isa-manual/src/unpriv/zcmt.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 9,681 |
[[ext:zbkc]]
=== ext:zbkc[] Extension for Carry-less Multiplication for Cryptography
Carry-less multiplication is the multiplication in the polynomial ring over
GF(2). [#norm:Zbkc_insns]#This extension is a subset of the ext:zbc[] extension, and only
provides insn:clmul[] and insn:clmulh[].# These are the crucial ins... | riscv-isa-manual/src/unpriv/zbkc.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 567 |
[[ext:zba]]
=== ext:zba[] Extension for Address Generation
The ext:zba[] instructions can be used to accelerate the generation of addresses that index into arrays of basic types (halfword, word, doubleword) using both unsigned word-sized and XLEN-sized indices: a shifted index is added to a base address.
The shift an... | riscv-isa-manual/src/unpriv/zba.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 1,565 |
[[unpriv-cfi]]
=== Control-Flow Integrity (CFI)
Control-flow integrity (CFI) capabilities help defend against Return-Oriented
Programming (ROP) and Call/Jump-Oriented Programming (COP/JOP) style
control-flow subversion attacks. These attack methodologies use code sequences
in authorized modules, with at least one inst... | riscv-isa-manual/src/unpriv/cfi.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 40,760 |
[[bits]]
== Bit Manipulation Extensions
NOTE: This chapter is currently being restructured.
Its contents are normative, but the presentation might appear disjoint.
The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture that are intended to pro... | riscv-isa-manual/src/unpriv/zb.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 56,872 |
[[ext:zicclsm]]
=== ext:zicclsm[] Extension for Main Memory Misaligned Accesses
[[norm:Zicclsm_misaligned_support]]
If the ext:zicclsm[] extension is implemented, then misaligned loads and stores
to main memory regions with both the coherence and cacheability PMAs must be
supported.
NOTE: This definition includes vec... | riscv-isa-manual/src/unpriv/zicclsm.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 609 |
[[app:mm-formal]]
=== Formal Memory Model Specifications, Version 0.1
To facilitate formal analysis of RVWMO, this chapter presents a set of
formalizations using different tools and modeling approaches. Any
discrepancies are unintended; the expectation is that the models
describe exactly the same sets of legal behavio... | riscv-isa-manual/src/unpriv/mm-formal.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 57,449 |
[[ext:zifencei]]
=== ext:zifencei[] Extension for Instruction-Fetch Fence
This chapter defines the ext:zifencei[] extension, which includes the
insn:fence.i[] instruction that provides explicit synchronization between writes
to instruction memory and instruction fetches on the same hart. Currently, this
instruction is ... | riscv-isa-manual/src/unpriv/zifencei.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 6,115 |
[[ext:zve32x]]
=== ext:zve32x[] Vector Extension for 32-bit Integer
This section describes ext:zve32x[], the vector extension for 8-, 16-,
and 32-bit integer and fixed-point types.
[#norm:Zve_xlen]#ext:zve32x[] is compatible with all currently defined base ISAs.#
The ext:zve32x[] extension requires that VLEN be at le... | riscv-isa-manual/src/unpriv/zve32x.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 1,436 |
[[ext:q]]
=== ext:q[] Extension for Quad-Precision Floating-Point
This chapter describes the ext:q[] standard extension for _quad-precision_
floating-point, which adds computational instructions compliant with the IEEE
754-2008 arithmetic standard's binary128 format and operations. The ext:q[] extension
depends on the... | riscv-isa-manual/src/unpriv/q-st-ext.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 5,348 |
[[ext:a]]
=== ext:a[] Extension for Atomic Instructions
[#norm:A_comprises]#The ext:a[] extension comprises the extlink:zalrsc[] and extlink:zaamo[] extensions,
which are defined in the following sections.#
[NOTE]
====
The instructions in the ext:a[] extension can be used to provide sequentially
consistent loads and ... | riscv-isa-manual/src/unpriv/a-st-ext.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 1,123 |
[[ext:zcd]]
=== ext:zcd[] Extension for Double-Precision Floating-Point Compressed Instructions
The ext:zcd[] extension adds compressed double-precision floating-point
load and store instructions.
[NOTE]
====
Double-precision loads and stores represent a significant fraction of static
instructions in programs compile... | riscv-isa-manual/src/unpriv/zcd.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 1,949 |
== Introduction
RISC-V (pronounced "`risk-five`") is a new instruction-set architecture
(ISA) that was originally designed to support computer architecture
research and education, but which we now hope will also become a
standard free and open architecture for industry implementations. Our
goals in defining RISC-V in... | riscv-isa-manual/src/unpriv/intro.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 36,898 |
[[ext:zcf]]
=== ext:zcf[] Extension for Single-Precision Floating-Point Compressed Instructions
The ext:zcf[] extension adds compressed single-precision floating-point
load and store instructions.
It is an XLEN=32-only extension.
[NOTE]
====
Single-precision loads and stores are not a significant source of static or
... | riscv-isa-manual/src/unpriv/zcf.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 3,314 |
[[ext:zawrs]]
=== ext:zawrs[] Extension for Wait-on-Reservation-Set instructions
The ext:zawrs[] extension defines a pair of insn:wrs[] (wait-on-reservation-set)
instructions to be used in polling loops that allows a core to enter a low-power
state and wait on a store to a memory location. Waiting for a memory locatio... | riscv-isa-manual/src/unpriv/zawrs.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 5,441 |
[[rv32]]
=== RV32I Base Integer Instruction Set
This section describes the RV32I base integer instruction set.
[NOTE]
====
RV32I was designed to be sufficient to form a compiler target and to
support modern operating system environments. The ISA was also designed
to reduce the hardware required in a minimal implement... | riscv-isa-manual/src/unpriv/rv32.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 49,842 |
[[ext:zvbc]]
=== ext:zvbc[] Vector Extension for Carry-less Multiplication
This extension provides carry-less multiplication instructions on vector
registers.
[#norm:Zvbc_dependent_Zve64x]#ext:zvbc[] depends upon the ext:zve64x[] extension.#
[#norm:Zvbc_sew64only]#The instructions in ext:zvbc[] are only defined for S... | riscv-isa-manual/src/unpriv/zvbc.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 4,921 |
[[ext:zimop]]
=== ext:zimop[] Extension for May-Be-Operations
This chapter defines the ext:zimop[] extension, which introduces the concept of
instructions that _may be operations_ (MOPs). MOPs are initially defined to
simply write zero to `x[rd]`, but are designed to be redefined by later
extensions to perform some o... | riscv-isa-manual/src/unpriv/zimop.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 3,098 |
[[ext:zkt]]
=== ext:zkt[] Extension for Data-Independent Execution Latency
The ext:zkt[] extension attests that the machine has data-independent execution
time for a safe subset of instructions. This property is commonly called
_"`constant-time`"_ although should not be taken with that literal meaning.
All currently ... | riscv-isa-manual/src/unpriv/zkt.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 15,254 |
[[ext:zca]]
=== ext:zca[] Extension for Integer Compressed Instructions
The compressed extensions use a simple compression scheme that offers shorter 16-bit versions
of common 32-bit RISC-V instructions when:
* the immediate or address offset is small, or
* one of the registers is the zero register (`x0`), the ABI li... | riscv-isa-manual/src/unpriv/zca.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 35,900 |
[[ext:zacas]]
=== ext:zacas[] Extension for Atomic Compare-and-Swap (CAS) Instructions
Compare-and-swap (CAS) provides an easy and typically faster way to perform
thread synchronization operations when supported as a hardware instruction. CAS
is typically used by lock-free and wait-free algorithms. This extension defi... | riscv-isa-manual/src/unpriv/zacas.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 7,867 |
[[ext:c]]
=== ext:c[] Extension for Compressed Instructions
This section describes the ext:c[] extension, which incorporates the
compressed instruction-set extensions designed for application-
and server-class processors.
The ext:c[] extension substantially improves code density across a wide
range of applications, th... | riscv-isa-manual/src/unpriv/c-st-ext.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 866 |
[[ext:zbc]]
=== ext:zbc[] Extension for Carry-less Multiplication
Carry-less multiplication is the multiplication in the polynomial ring over GF(2).
[#norm:Zbc_clmul_clmulh_results]#insn:clmul[] produces the lower half of the carry-less product and insn:clmulh[] produces the upper half of the 2{times}XLEN carry-less ... | riscv-isa-manual/src/unpriv/zbc.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 716 |
[[ext:v]]
=== ext:v[] Vector Extension for Application Processors
The single-letter V extension is intended for use in application
processor profiles.
[#norm:misa_v_op]#The csr:misa[v] bit is set for implementations providing csr:misa[] and
supporting V.#
[#norm:V_precise_traps]#The V vector extension has precise tr... | riscv-isa-manual/src/unpriv/v-st-ext.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 2,997 |
[[ext:zvbb]]
=== ext:zvbb[] Vector Extension for Basic Bit Manipulation
This extension provides basic bit-manipulation instructions on vector registers.
[#norm:Zvbb_dependent_Zve32x]#ext:zvbb[] depends upon the ext:zve32x[] extension.#
[#norm:Zvbb_eew]#ext:zvbb[] provides support for EEW of 8, 16, and 32.#
[#norm:Zvb... | riscv-isa-manual/src/unpriv/zvbb.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 16,145 |
[[ext:zvfbfmin]]
=== ext:zvfbfmin[] Vector Extension for BF16 Conversions
This extension provides the minimal set of instructions needed to enable vector support of the BF16
format. It enables BF16 as an interchange format as it provides conversion between BF16 values
and FP32 values.
[[norm:Zvfbfmin_depends_Zve32f]]... | riscv-isa-manual/src/unpriv/zvfbfmin.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 4,447 |
[[ext:d]]
=== ext:d[] Extension for Double-Precision Floating-Point
(((double-precision, floating point)))
(((floating point, double precision)))
This chapter describes the ext:d[] standard extension for _double-precision_
floating-point, which adds computational instructions compliant with the IEEE
754-2008 arithmeti... | riscv-isa-manual/src/unpriv/d-st-ext.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 11,538 |
[[ext:zve64d]]
=== ext:zve64d[] Vector Extension for Double-Precision Floating-Point
This section describes ext:zve64d[], the vector extension for
double-precision floating-point.
It is compatible with all currently defined base ISAs.
[#norm:Zve64d_dependent_Zve64f]#The ext:zve64d[] extension depends on the ext:zve64... | riscv-isa-manual/src/unpriv/zve64d.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 908 |
[[zf]]
== Scalar Floating-Point Extensions
NOTE: This chapter is currently being restructured.
Its contents are normative, but the presentation might appear disjoint.
This chapter describes the scalar floating-point extensions.
The extlink:f[] extension adds floating-point registers and
instructions for computation o... | riscv-isa-manual/src/unpriv/zf.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 2,470 |
[[ext:zcb]]
=== ext:zcb[] Extension for Additional Compressed Instructions
The ext:zcb[] extension adds several compressed instructions which, like those
in the extlink:zca[] extension, expand into a single 32-bit instruction.
The ext:zcb[] extension depends on the ext:zca[] extension.
As shown on the individual inst... | riscv-isa-manual/src/unpriv/zcb.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 14,531 |
[[rv64]]
=== RV64I Base Integer Instruction Set
This section describes the RV64I base integer instruction set, which
builds upon the RV32I variant described in <<rv32>>.
This chapter presents only the differences with RV32I, so should be read
in conjunction with the earlier chapter.
==== Register State
[#norm:rv64i_... | riscv-isa-manual/src/unpriv/rv64.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 9,963 |
[[ext:zcmop]]
=== ext:zcmop[] Extension for Compressed May-Be-Operations
[#norm:Zcmop_op]#This section defines the ext:zcmop[] extension, which defines eight 16-bit MOP
instructions named insn:c.mop.n[], where N is an odd integer between 1 and
15, inclusive.# [#norm:Zcmop_enc]#insn:c.mop.n[] is encoded in the reserve... | riscv-isa-manual/src/unpriv/zcmop.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 1,896 |
[[rvbna]]
=== RISC-V Bulk Normalization Algorithm
This section defines the RISC-V Bulk Normalization Algorithm (RVBNA), a scheme
employed by multiple RISC-V extensions for efficient computation of
floating-point dot products.
A correctly rounded dot product is costly, and many applications do not
require such a degre... | riscv-isa-manual/src/unpriv/rvbna.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 18,591 |
[[zvk]]
=== Vector Cryptography Extensions
This chapter describes the vector cryptography extensions to the RISC-V ISA.
[[crypto_vector_introduction]]
==== Introduction
This chapter describes the RISC-V _vector_ cryptography extensions.
All instructions described here are based on the Vector registers.
The instructi... | riscv-isa-manual/src/unpriv/zvk.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 118,683 |
[[app:vector-examples]]
=== Vector Assembly Code Examples
The following are provided as non-normative text to help explain the vector ISA.
==== Vector-vector add example
----
include::example/vvaddint32.s[lines=4..-1]
----
==== Example with mixed-width mask and compute.
----
# Code using one width for predicate an... | riscv-isa-manual/src/unpriv/vector-examples.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 9,038 |
[appendix]
[[app:rationale]]
== Historical Rationale for Extensions
This appendix contains the rationale for RISC-V ISA extensions at the time they
were ratified.
Unlike the ISA specification, this appendix is ordered chronologically, so as
to convey the motivation and architectural reasoning underpinning each
extensi... | riscv-isa-manual/src/unpriv/rationale.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 9,500 |
[[vol:unpriv]]
[volume=I]
= The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture
include::preface.adoc[]
include::intro.adoc[]
include::base.adoc[]
include::memory-models.adoc[]
include::zi.adoc[]
include::za.adoc[]
include::zf.adoc[]
include::zc.adoc[]
include::zb.adoc[]
include::zv.adoc[]
include:... | riscv-isa-manual/src/unpriv/unpriv.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 550 |
[[ext:ziccif]]
=== ext:ziccif[] Extension for Instruction-Fetch Atomicity
NOTE: This extension was ratified alongside the RVA20U64 profile.
This chapter supplies an operational definition for the extension
and adds expository material.
[[norm:Ziccif_if_atomicity]]
If the ext:ziccif[] extension is implemented, main me... | riscv-isa-manual/src/unpriv/ziccif.adoc | docs | riscv-isa-manual | CC-BY-4.0 | CC-BY-4.0 | e17d92a1cbc06d5281d483eed670a010c27aa26c | false | 3,138 |
<!--
Copyright 2021, seL4 Project a Series of LF Projects, LLC
SPDX-License-Identifier: CC-BY-SA-4.0
-->
# seL4 Reference Manual
## Build
To build a PDF use
make
You will need recent version of `LaTeX` and `doxygen` as well as the seL4 python
dependencies.
The main source file is `manual.tex`, most... | sel4-doc/manual/README.md | docs | sel4-doc | GPL-2.0 | GPL-2.0 | 97bd522e831086fbc68dbc0fef0ab0eefc710eae | false | 8,945 |
%
% Copyright 2014, General Dynamics C4 Systems
%
% SPDX-License-Identifier: GPL-2.0-only
%
\documentclass[english,a4paper,11pt,twoside]{report}
\usepackage{sel4}
\usepackage[authoryear]{natbib}
\def\cite{\citep}
\newif \ifxeightsix \xeightsixtrue
\usepackage{url}
% Glossary
\usepackage[acronym,toc]{glossaries}
\... | sel4-doc/manual/manual.tex | docs | sel4-doc | GPL-2.0 | GPL-2.0 | 97bd522e831086fbc68dbc0fef0ab0eefc710eae | false | 4,651 |
%
% Copyright 2014, General Dynamics C4 Systems
%
% SPDX-License-Identifier: GPL-2.0-only
%
\chapter{\label{ch:io}Hardware I/O}
\section{Interrupt Delivery}
\label{sec:interrupts}
Interrupts are delivered as notifications. A thread
may configure the kernel to signal a particular \obj{Notification}
object each time a... | sel4-doc/manual/parts/io.tex | docs | sel4-doc | GPL-2.0 | GPL-2.0 | 97bd522e831086fbc68dbc0fef0ab0eefc710eae | false | 25,000 |
%
% Copyright 2014, General Dynamics C4 Systems
%
% SPDX-License-Identifier: GPL-2.0-only
%
%macros for API documentation
\newcommand{\param}[3]{\texttt{#1}&\texttt{#2}\\ }
\newcommand{\errortable}[1]{
\begin{center}
\begin{minipage}{0.95\textwidth}
\begin{tabularx}{\textwidth}{lX}
\toprule
\te... | sel4-doc/manual/parts/api.tex | docs | sel4-doc | GPL-2.0 | GPL-2.0 | 97bd522e831086fbc68dbc0fef0ab0eefc710eae | false | 9,294 |
%
% Copyright 2014, General Dynamics C4 Systems
%
% SPDX-License-Identifier: GPL-2.0-only
%
\chapter{\label{ch:intro}Introduction}
% FIXME: Use of service, mechanism and abstraction is munged through the rest of the manual
The seL4 microkernel is an operating-system kernel designed to be a secure,
safe, and reliable... | sel4-doc/manual/parts/intro.tex | docs | sel4-doc | GPL-2.0 | GPL-2.0 | 97bd522e831086fbc68dbc0fef0ab0eefc710eae | false | 2,307 |
%
% Copyright 2014, General Dynamics C4 Systems
%
% SPDX-License-Identifier: GPL-2.0-only
%
\chapter{\label{ch:ipc}Message Passing (IPC)}
The seL4 microkernel provides a message-passing IPC mechanism for communication
between threads. The same mechanism is also used for communication with
kernel-provided services. Me... | sel4-doc/manual/parts/ipc.tex | docs | sel4-doc | GPL-2.0 | GPL-2.0 | 97bd522e831086fbc68dbc0fef0ab0eefc710eae | false | 15,042 |
%
% Copyright 2014, General Dynamics C4 Systems
%
% SPDX-License-Identifier: GPL-2.0-only
%
\chapter{\label{ch:cspace}Capability Spaces}
Recall from \autoref{sec:cap-access-control} that seL4 implements a
capability-based access control model. Each userspace thread has an
associated \emph{capability space} (CSpace) ... | sel4-doc/manual/parts/cspace.tex | docs | sel4-doc | GPL-2.0 | GPL-2.0 | 97bd522e831086fbc68dbc0fef0ab0eefc710eae | false | 26,285 |
%
% Copyright 2014, General Dynamics C4 Systems
%
% SPDX-License-Identifier: GPL-2.0-only
%
\chapter{\label{ch:notifications}Notifications}
Notifications are a simple, non-blocking signalling mechanism that
logically represents a set of binary semaphores.
\section{Notification Objects}
A \obj{Notification} object c... | sel4-doc/manual/parts/notifications.tex | docs | sel4-doc | GPL-2.0 | GPL-2.0 | 97bd522e831086fbc68dbc0fef0ab0eefc710eae | false | 3,078 |
%
% Copyright 2014, General Dynamics C4 Systems
%
% SPDX-License-Identifier: GPL-2.0-only
%
\newglossaryentry{asid}{
name=ASID,
description={Address Space Identifier. Depending on architecture, the kernel provides software ASIDs, which are associated with VSpace root objects, and define the virtual address spa... | sel4-doc/manual/parts/glossary.tex | docs | sel4-doc | GPL-2.0 | GPL-2.0 | 97bd522e831086fbc68dbc0fef0ab0eefc710eae | false | 6,030 |
%
% Copyright 2014, General Dynamics C4 Systems
%
% SPDX-License-Identifier: GPL-2.0-only
%
\chapter{\label{ch:threads}Threads and Execution}
\section{Threads}
\label{sec:threads}
seL4 provides threads to represent an execution context. On MCS configurations of
the kernel, scheduling contexts are used to manage pro... | sel4-doc/manual/parts/threads.tex | docs | sel4-doc | GPL-2.0 | GPL-2.0 | 97bd522e831086fbc68dbc0fef0ab0eefc710eae | false | 43,137 |
%
% Copyright 2014, General Dynamics C4 Systems
%
% SPDX-License-Identifier: GPL-2.0-only
%
\chapter{\label{ch:bootup}System Bootstrapping}
\section{Initial Thread's Environment}
The seL4 kernel creates a minimal boot environment for the initial thread, which
is started at priority \texttt{seL4\_MaxPrio} and maximu... | sel4-doc/manual/parts/bootup.tex | docs | sel4-doc | GPL-2.0 | GPL-2.0 | 97bd522e831086fbc68dbc0fef0ab0eefc710eae | false | 12,892 |
%
% Copyright 2014, General Dynamics C4 Systems
%
% SPDX-License-Identifier: GPL-2.0-only
%
\chapter{\label{ch:vspace}Address Spaces and Virtual Memory}
A virtual address space in seL4 is called a VSpace. Similarly to a CSpace (see \autoref{ch:cspace}),
a VSpace is composed of objects provided by the kernel. Unlike C... | sel4-doc/manual/parts/vspace.tex | docs | sel4-doc | GPL-2.0 | GPL-2.0 | 97bd522e831086fbc68dbc0fef0ab0eefc710eae | false | 19,366 |
%
% Copyright 2014, General Dynamics C4 Systems
%
% SPDX-License-Identifier: GPL-2.0-only
%
\chapter{\label{ch:objects}Kernel Services and Objects}
A limited number of service primitives are provided by the microkernel;
more complex services may be implemented as applications on top of these
primitives. In this way, ... | sel4-doc/manual/parts/objects.tex | docs | sel4-doc | GPL-2.0 | GPL-2.0 | 97bd522e831086fbc68dbc0fef0ab0eefc710eae | false | 26,234 |
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